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Intel pushes FPGAs into the data center

Modern FPGAs can speed up a wide range of applications, but they still require a lot of expertise. Intel aims to make it easier for the rest of the world to use programmable logic for server acceleration.

When it comes to speeding up computationally intensive workloads, GPUs are not the only game in town. FPGAs (field-programmable gate arrays) are also gaining traction in data centers.

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These programmable logic devices, which can be reconfigured “in the field” for different tasks after manufacturing, have long been used in telecom gear, industrial systems, automotive, and military and aerospace applications. But modern FPGAs with large gate arrays, memory blocks, and fast IO are suitable for a wide range of tasks.

Microsoft has been using Altera FPGAs in its servers to run many of the neural networks behind services such as Bing searches, Cortana speech recognition, and natural-language translation. At the Hot Chips conference in August, Microsoft announced Project Brainwave, which will make FPGAs available as an Azure service for inferencing. Baidu is also working on FPGAs in its data center and AWS already offers EC2 F1 instances with Xilinx Virtex UltraScale+ FPGAs.

Most customers buy FPGAs as chips, and then design their own hardware and program them in a hardware description language such as VHDL or Verilog. Over time, some FPGAs have morphed into SoCs with ARM CPUs, hard blocks for memory and IO, and more (this week Xilinx just announced a family of Zync UltraScale+ FPGAs with a quad-core Cortex-A53 and the RF data converters for 5G wireless and cable). But the fact remains that FPGAs require considerable hardware and software engineering resources.

“One of the strengths of FPGAs is that they are infinitely flexible, but it is also one of their biggest challenges,” said Nicola Tan, senior marketing manager for data center solutions in Intel’s Programmable Solutions Group.

Now Intel is aiming to make it easier for other businesses to use FPGAs as server accelerators. This week the chipmaker announced the first of a new family of standard Programmable Acceleration Cards (PACs) for Xeon servers as well as software that makes them easier to program. In addition, Intel and partners are building functions for a wide variety of applications including encryption, compression, network packet processing, database acceleration, video streaming analytics, genomics, finance, and, of course, machine learning.

The PAC is a standard PCI Express Gen3 expansion card that can be plugged into any server. The first card combines the Arria 10 GX, a mid-range FPGA manufactured on TSMC’s 20nm process, with 8GB of DDR4 memory and 128MB of flash. It is currently sampling and will ship in the first half of 2018. Intel said it will also offer a PAC with the high-end Stratix 10, manufactured on its own 14nm process, but it hasn’t said when that version will be available.

At Hot Chips in August, Microsoft provided a sneak preview of the kind of performance that the Stratix 10 can deliver in the data center and said it expects a production-level chip running at 500MHz with tuned software will deliver a whopping 90 teraops (trillions of operations per second) for AI inferencing using its custom data format.

In addition to the PACs, Intel will also offer an MCP (multi-chip package) that combines a Skylake Xeon Scalable Processor and an FPGA. This is something Intel has been talking up since the $16.7 billion acquisition of Altera, and it has previously shown test chips with Broadwell Xeons and FPGAs, but the first commercial chip will arrive in the second half of 2018.

Conceptually, this isn’t really all that different from the Altera and Xilinx SoCs that already include ARM CPUs, but x86 processors should deliver higher performance and Intel can leverage the proprietary interconnect and 2.5D packaging technologies it has been developing.

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